Very Cute Data

Description

This challenge aims to introduce you to the analysis of digital signal captures using a logic analyzer. The provided capture is in the vcd format (for Value Change Dump, see here for more information), and you can open it with software like pulseview or GTKWave for signal visualization. For manipulation of these files, you can use the Python library pyDigitalWaveTools.vcd, among other existing libraries.

The capture consists of two digital signals, D0 and D1: the first corresponds to binary data, and the second is a clock. In many communication bus protocols, digital signals represent “sampled” data on clock edges. This challenge will help you become familiar with this concept. The data signal of interest here, namely D0̀, is sampled on the falling edges of the clock: when D1 transitions from 1 to 0, the state of D0 corresponds to the value to be retained at that time sample.

You are tasked with extracting the “sampled” binary data between the sample at 350 microseconds and the sample at 2000 microseconds. The result is a bit string B that should be provided in the format FCSC{B} as the flag. As an example, sampling between the sample at 0 and the sample at 350 microseconds would yield FCSC{1000100010}.

We strongly advise automating this extraction, as it will be very useful for other challenges in the hardware category!